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hyb25d256400/800at 256-mbit double data rata sdram 10/01 page 1 of 75 features ? double data rate architecture: two data transfers per clock cycle bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver dqs is edge-aligned with data for reads and is center-aligned with data for writes differential clock inputs (ck and ck ) four internal banks for concurrent operation data mask (dm) for write data dll aligns dq and dqs transitions with ck transitions. commands entered on each positive ck edge; data and data mask referenced to both edges of dqs burst lengths: 2, 4, or 8 cas latency: 2, 2.5 auto precharge option for each burst access auto refresh and self refresh modes 7.8 s maximum average periodic refresh interval 2.5v (sstl_2 compatible) i/o v ddq = 2.5v 0.2v / v dd = 2.5v 0.2v tsop66 package description the 256mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram. the 256mb ddr sdram uses a double-data-rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr sdram effectively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one- half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 256mb ddr sdram operates from a differen- tial clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the posi- tive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, thereby providing high effective band- width by hiding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all inputs are compatible with the jedec standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. cas latency and frequency cas latency maximum operating frequency (mhz) ddr266a -7 ddr200 -8 2133100 2.5 143 125
hyb25d256400/800at 256-mbit double data rate sdram page 2 of 75 10/01 pin configuration 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc nc nc dq2 v ddq nc nc v dd nu nc we cas ras cs nc ba0 ba1 v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc nc nc dq5 v ssq dqs nc v ref v ss dm* ck ck cke nc a12 a11 a9 v dd nc v ddq nc dq0 v ssq v ddq nc dq1 v ssq nc nc nc nc v ddq nc nc v dd nu nc we cas ras cs nc ba0 ba1 v ss nc v ssq nc dq3 v ddq v ssq nc dq2 v ddq nc nc nc nc v ssq dqs nc v ref v ss dm* ck ck cke nc a12 a11 a9 a10/ap a0 a1 a2 a3 v dd a10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss a8 a7 a6 a5 a4 v ss column address table organization column address 64mb x 4 a0-a9, a11 32mb x 8 a0-a9 * dm is internally loaded to match dq and dqs identically . i 64mb x 4 32mb x 8 66-pin plastic tsop-ii 400mil
hyb25d256400/800at 256-mbit double data rate sdram page 3 of 75 10/01 input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sam- pled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asyn- chronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power-down. input buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for exter- nal bank selection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 - a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. dq input/output data input/output: data bus. dqs input/output data strobe: output with read data, input with write data. edge-aligned with read data, cen- tered in write data. used to capture write data. nc no connect: no internal electrical connection is present. nu don?t use v ddq supply dq power supply: 2.5v 0.2v. v ssq supply dq ground v dd supply power supply: 2.5v 0.2v. v ss supply ground v ref supply sstl_2 reference voltage: (v ddq / 2)
hyb25d256400/800at 256-mbit double data rate sdram page 4 of 75 10/01 ordering information part numbers standard versions cas latency clock (mhz) cas latency clock (mhz) speed org. package HYB25D256400AT-7 2.5 143 2 133 ddr266a x 4 66 pin tsop-ii hyb25d256800at-7 x 8 hyb25d256400at-8 125 100 ddr200 x 4 hyb25d256800at-8 x 8
hyb25d256400/800at 256-mbit double data rate sdram page 5 of 75 10/01 block diagram (64mb x 4) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 11 command decode a0-a12, ba0, ba1 cke 13 15 i/o gating dm mask logic bank0 memory array (8192 x 1024 x 8) sense amplifiers bank1 bank2 bank3 13 10 1 2 2 refresh counter 4 4 4 input register 1 1 1 1 1 8 8 2 8 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 4 4 4 4 4 8 dq0-dq3, dm dqs 1 read latch write fifo & drivers note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals. column decoder 1024 (x8) row-address mux registers 13 8192 bank0 row-address latch & decoder 8192 address register drivers bank control logic 15 ck
hyb25d256400/800at 256-mbit double data rate sdram page 6 of 75 10/01 block diagram (32mb x 8) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 10 command decode a0-a12, ba0, ba1 cke 15 15 i/o gating dm mask logic bank0 memory array (8192 x 512 x 16) sense amplifiers bank1 bank2 bank3 13 9 1 2 2 refresh counter 8 8 8 input register 1 1 1 1 1 16 16 2 16 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 8 8 8 8 8 16 dq0-dq7, dm dqs 1 read latch write fifo & drivers note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals. column decoder 512 (x16) row-address mux registers 13 8192 bank0 row-address latch & decoder 8192 address register drivers bank control logic 13 ck
hyb25d256400/800at 256-mbit double data rate sdram page 7 of 75 10/01 functional description the 256mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 268, 435, 456 bits. the 256mb ddr sdram is internally configured as a quad-bank dram. the 256mb ddr sdram uses a double-data-rate architecture to achieve high-speed operation. the double- data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr sdram consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a12 select the row). the address bits registered coincident with the read or write com- mand are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device operation. initialization ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following two conditions must be met: no power sequencing is specified during power up or power down given the following criteria: v dd and v ddq are driven from a single power converter output v tt meets the specification a minimum resistance of 42 ohms limits the input current from the v tt supply into any pin and v ref tracks v ddq /2 or the following relationship must be followed: v ddq is driven after or with v dd such that v ddq < v dd + 0.3 v v tt is driven after or with v ddq such that v tt < v ddq + 0.3v v ref is driven after or with v ddq such that v ref < v ddq + 0.3v the dq and dqs outputs are in the high-z state, where they remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a mode register set command should be issued for the extended mode register, to enable the dll, then a mode register set command should be issued for the mode register, to reset the dll, and to program the operat- ing parameters. 200 clock cycles are required between the dll reset and any executable command. during the 200 cyalces of clock for dll locking, a delect or nop command must be appied. after the 200 clock cycles, a precharge all command should be applied, placing the device in the ? all banks idle ? state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated (i.e. to program operating parameters without resetting the dll) must be performed. following these cycles, the ddr sdram is ready for normal operation.
hyb25d256400/800at 256-mbit double data rate sdram page 8 of 75 10/01 register definition mode register the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode. the mode reg- ister is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). mode register bits a0-a2 specify the burst length, a3 specifies the type of burst (sequential or interleaved), a4-a6 specify the cas latency, and a7-a12 specify the operating mode. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements results in unspecified opera- tion. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts.
hyb25d256400/800at 256-mbit double data rate sdram page 9 of 75 10/01 mode register operation a8 a7 a6 a5 a4 cas latency a3 a2 a1 a0 burst length bt address bus cas latency a6 a5 a4 latency 000 reserved 001 reserved 010 2 011 reserved 100 reserved 101 reserved 110 2.5 1 1 1 reserved burst length a2 a1 a0 burst length 000 reserved 001 2 010 4 011 8 100 reserved 101 reserved 110 reserved 111 reserved ba1 ba0 a11 a10 a9 0* 0* mode register operating mode * ba0 and ba1 must be 0, 0 to select the mode register (vs. the extended mode register). a12 - a9 a8 a7 a6 - a0 operating mode 000valid normal operation do not reset dll 010valid normal operation in dll reset 0 0 1 reserved ??? reserved a3 burst type 0 sequential 1 interleave vs ** vendor specific a12
hyb25d256400/800at 256-mbit double data rate sdram page 10 of 75 10/01 notes: 1. for a burst length of two, a1-ai selects the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definition on page 10. read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 2 or 2.5 clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. burst definition burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 2 0 0-1 0-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
hyb25d256400/800at 256-mbit double data rate sdram page 11 of 75 10/01 operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a12 to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. a mode register set command issued to reset the dll should always be followed by a mode register set command to select normal operating mode. all other combinations of values for a7-a12 are reserved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. required cas latencies nop nop nop nop nop read cas latency = 2, bl = 4 shown with nominal t ac , t dqsck , and t dqsq . ck ck command dqs dq don ? t care cl=2 nop nop nop nop nop read cas latency = 2.5, bl = 4 ck ck command dqs dq cl=2.5
hyb25d256400/800at 256-mbit double data rate sdram page 12 of 75 10/01 extended mode register the extended mode register controls functions beyond those controlled by the mode register; these addi- tional functions include dll enable/disable and output drive strength selection (for future design versions, not implement in this product). these functions are controlled via the bits shown in the extended mode register definition. the extended mode register is programmed via the mode register set command (with ba0 = 1 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements result in unspecified operation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. this is the reason 200 clock cycles must occur before issuing a read or write command upon exit of self refresh operation. output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. i-v curves for the normal drive strength are included in this document. an option for weak driver support intended for lighter load and/or point-to-point environments and will be implemented in future versions of this product. selection of the weak driver option will reduce the output drive strength by ~ 55% of that of the normal strength.
hyb25d256400/800at 256-mbit double data rate sdram page 13 of 75 10/01 extended mode register definition a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address bus drive strength a 1 drive strength 0normal 1reserved ba1 ba0 operating mode a 11 a 10 a 9 0 * 1 * * ba0 and ba1 must be 1, 0 to select the extended mode register mode register extended ds dll a 0 dll 0 enable 1 disable an - a3 a2 - a0 operating mode 0 valid normal operation ?? all other states reserved (vs. the base mode register) a 12 0 ** 0** has to programmed to 0
hyb25d256400/800at 256-mbit double data rate sdram page 14 of 75 10/01 commands commandsdeselect the deselect function prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to a ddr sdram. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a0-a12, ba0 and ba1. see mode register descriptions in the reg- ister definition section. the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge (or read or write with auto precharge) is issued to that bank. a precharge (or read or write with auto precharge) command must be issued and com- pleted before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 8, j = don ? t care] for x16, [i = 9, j = don ? t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. write the write command is used to initiate a burst write access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 9, j = don ? t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coin- cident with the data. if a given dm signal is registered low, the corresponding data is written to memory; if the dm signal is registered high, the corresponding data inputs are ignored, and a write is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ? don ? t care. ? once a bank has been precharged, it is in the idle state and must be activated prior to any
hyb25d256400/800at 256-mbit double data rate sdram page 15 of 75 10/01 read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto pre- charge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most re- cently registered read command prior to the burst terminate command is truncated, as shown in the opera- tion section of this data sheet. auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas before ras (cbr) refresh in previous dram types. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ? don ? t care ? during an auto refresh command. the 256mb ddr sdram requires auto refresh cycles at an aver- age periodic interval of 7.8 s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted in the system, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 * 7.8 s (70.2 s). this maximum absolute interval is short enough to allow for dll updates internal to the ddr sdram to be restricted to auto refresh cycles, without allowing too much drift in t ac between updates. self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated as an auto refresh command coincident with cke transitioning low. the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except cke (low) are ? don ? t care ? during self refresh operation. the procedure for exiting self refresh requires a sequence of commands. ck (and ck ) must be stable prior to cke returning high. once cke is high, the sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other command.
hyb25d256400/800at 256-mbit double data rate sdram page 16 of 75 10/01 truth table 1a: commands name (function) cs ras cas we address mne notes deselect (nop) h x x x x nop 1, 9 no operation (nop) l h h h x nop 1, 9 active (select bank and activate row) l l h h bank/row act 1, 3 read (select bank and column, and start read burst) l h l h bank/col read 1, 4 write (select bank and column, and start write burst) l h l l bank/col write 1, 4 burst terminate l h h l x bst 1, 8 precharge (deactivate row in bank or banks) l l h l code pre 1, 5 auto refresh or self refresh (enter self refresh mode) l l l h x ar / sr 1, 6, 7 mode register set l l l l op-code mrs 1, 2 1. cke is high for all commands shown except self refresh. 2. ba0, ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a12 provide the op-code to be written to the selected mode register.) 3. ba0-ba1 provide bank address and a0-a12 provide row address. 4. ba0, ba1 provide bank address; a0-a i provide column address (where i = 9 for x8 and 9, 11 for x4); a10 high enables the auto precharge feature (nonpersistent), a10 low disables the auto precharge feature. 5. a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row and bank addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts 9. deselect and nop are functionally interchangeable. truth table 1b: dm operation name (function) dm dqs notes write enable l valid 1 write inhibit h x 1 1. used to mask write data; provided coincident with the corresponding data.
hyb25d256400/800at 256-mbit double data rate sdram page 17 of 75 10/01 operations bank/row activation before any read or write commands can be issued to a bank within the ddr sdram, a row in that bank must be ? opened ? (activated). this is accomplished via the active command and addresses a0-a12, ba0 and ba1 (see activating a specific row in a specific bank), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ? closed ? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active com- mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd . activating a specific row in a specific bank ra ba high ra = row address. ba = bank address. ck ck cke cs ras cas we a0-a12 ba0, ba1 don ? t care
hyb25d256400/800at 256-mbit double data rate sdram page 18 of 75 10/01 reads subsequent to programming the mode register with cas latency, burst type, and burst length, read bursts are initiated with a read command, as shown on read command on page 19. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row that is accessed starts pre- charge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address is available following the cas latency after the read command. each subsequent data-out element is valid nominally at the next posi- tive or negative clock edge (i.e. at the next crossing of ck and ck ). read burst: cas latencies (burst length = 4) on page 20 shows general timing for each supported cas latency setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. upon completion of a burst, assuming no other commands have been initiated, the dqs goes high-z. data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). this is shown on consecutive read bursts: cas latencies (burst length = 4 or 8) on page 21. a read command can be initiated on any clock cycle following a previous read command. nonconsecutive read data is illustrated on non-consecutive read bursts: cas latencies (burst length = 4) on page 22. full-speed random read accesses: cas latencies (burst length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 23. t rcd and t rrd definition row act nop col row ba y ba y ba x act nop nop ck ck command a0-a12 ba0, ba1 don ? t care rd/wr t rcd t rrd rd/wr nop nop
hyb25d256400/800at 256-mbit double data rate sdram page 19 of 75 10/01 read command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don ? t care ca x4: a0-a9, a11 x8: a0-a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
hyb25d256400/800at 256-mbit double data rate sdram page 20 of 75 10/01 read burst: cas latencies (burst length = 4) cas latency = 2 nop nop nop nop nop read ck ck command address dqs dq cas latency = 2.5 don ? t care ba a,col n doa-n cl=2.5 nop nop nop nop nop read ck ck command address dqs dq ba a,col n doa-n do a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . cl=2
hyb25d256400/800at 256-mbit double data rate sdram page 21 of 75 10/01 consecutive read bursts: cas latencies (burst length = 4 or 8) cas latency = 2 nop read nop nop nop read ck ck command address dqs dq cl=2 baa, col n baa, col b don ? t care do a-n (or a-b) = data out from bank a, column n (or bank a, column b). when burst length = 4, the bursts are concatenated. when burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following do a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following do a-b. shown with nominal t ac , t dqsck , and t dqsq . cas latency = 2.5 nop read nop nop nop read ck ck command address dqs dq cl=2.5 baa, col n baa,col b doa-n doa- n doa- b doa-b
hyb25d256400/800at 256-mbit double data rate sdram page 22 of 75 10/01 non-consecutive read bursts: cas latencies (burst length = 4) cas latency = 2 nop nop read nop nop read ck ck command address dqs dq do a-n doa- b do a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following do a-n (and following do a-b). shown with nominal t ac , t dqsck , and t dqsq . don ? t care baa, col n baa, col b cl=2 cas latency = 2.5 nop nop read nop nop read do a-n doa- b baa, col n baa, col b cl=2.5 ck ck command address dqs dq nop
hyb25d256400/800at 256-mbit double data rate sdram page 23 of 75 10/01 random read accesses: cas latencies (burst length = 2, 4 or 8) doa-n cas latency = 2 read read read nop nop read doa-b doa-n ? doa-x doa-x ? doa-b ? doa-g ck ck command address dqs dq do a-n, etc. = data out from bank a, column n etc. n ? etc. = odd or even complement of n, etc. (i.e., column address lsb inverted). reads are to active rows in any banks. shown with nominal t ac , t dqsck , and t dqsq . don ? t care baa, col n baa, col x baa, col b baa, col g cl=2 doa-n cas latency = 2.5 read read read nop nop read doa-b doa-n ? doa-x doa-x ? doa-b ? ck ck command address dqs dq baa, col n baa, col x baa, col b baa, col g cl=2.5
hyb25d256400/800at 256-mbit double data rate sdram page 24 of 75 10/01 data from any read burst may be truncated with a burst terminate command, as shown on terminating a read burst: cas latencies (burst length = 8) on page 25. the burst terminate latency is equal to the read (cas) latency, i.e. the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs. data from any read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown on read to write: cas latencies (burst length = 4 or 8) on page 26. the example is shown for t dqss (min). the t dqss (max) case, not shown here, has a longer bus idle time. t dqss (min) and t dqss (max) are defined in the section on writes. a read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated). the precharge command should be issued x cycles after the read com- mand, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch archi- tecture). this is shown on read to precharge: cas latencies (burst length = 4 or 8) on page 27 for read latencies of 2 and 2.5. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto pre- charge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
hyb25d256400/800at 256-mbit double data rate sdram page 25 of 75 10/01 terminating a read burst: cas latencies (burst length = 8) cas latency = 2 nop bst nop nop nop read ck command address dqs dq do a-n = data out from bank a, column n. cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . doa-n don ? t care ck baa, col n cl=2 cas latency = 2.5 nop bst nop nop nop read ck command address dqs dq doa-n ck baa, col n cl=2.5 no further output data after this point. dqs tristated. no further output data after this point. dqs tristated.
hyb25d256400/800at 256-mbit double data rate sdram page 26 of 75 10/01 read to write: cas latencies (burst length = 4 or 8) cas latency = 2 bst nop write nop nop read di a-b ck ck command address dqs dq dm doa-n do a-n = data out from bank a, column n 1 subsequent elements of data out appear in the programmed order following do a-n. data in elements are applied following dl a-b in the programmed order, according to burst length. don ? t care baa, col n baa, col b cl=2 t dqss (min) cas latency = 2.5 bst nop nop write nop read ck ck command address dqs dq dm doa-n baa, col n baa, col b cl=2.5 t dqss (min) dla-b shown with nominal t ac , t dqsck , and t dqsq . . di a-b = data in to bank a, column b
hyb25d256400/800at 256-mbit double data rate sdram page 27 of 75 10/01 read to precharge: cas latencies (burst length = 4 or 8) cas latency = 2 nop pre nop nop act read ck ck command address dqs dq doa-n do a-n = data out from bank a, column n. cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . don ? t care ba a, col n ba a or all ba a, row cl=2.5 cas latency = 2.5 nop pre nop nop act read ck ck command address dqs dq doa-n t rp ba a, col n ba a or all ba a, row cl=2 t rp
hyb25d256400/800at 256-mbit double data rate sdram page 28 of 75 10/01 writes write bursts are initiated with a write command, as shown on write command on page 29. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the following illustrations, auto pre- charge is disabled. during write bursts, the first valid data-in element is registered on the first rising edge of dqs following the write command, and subsequent data elements are registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write com- mand and the first corresponding rising edge of dqs (t dqss ) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the write diagrams that follow are drawn for the two extreme cases (i.e. t dqss (min) and t dqss (max)). write burst (burst length = 4) on page 30 shows the two extremes of t dqss for a burst of four. upon completion of a burst, assuming no other commands have been initiated, the dqs and dqs enters high-z and any additional input data is ignored. data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any pos- itive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). write to write (burst length = 4) on page 31 shows concatenated bursts of 4. an example of non-consecutive writes is shown on write to write: max dqss, non-consecutive (burst length = 4) on page 32. full-speed random write accesses within a page or pages can be performed as shown on random write cycles (burst length = 2, 4 or 8) on page 33. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr (write to read) should be met as shown on write to read: non- interrupting (cas latency = 2; burst length = 4) on page 34. data for any write burst may be truncated by a subsequent read command, as shown in the figures on write to read: interrupting (cas latency = 2; burst length = 8) on page 35 to write to read: nominal dqss, inter- rupting (cas latency = 2; burst length = 8) on page 37. note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in must be masked with dm, as shown in the diagrams noted previously. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met as shown on write to precharge: non-interrupting (burst length = 4) on page 38. data for any write burst may be truncated by a subsequent precharge command, as shown in the figures on write to precharge: interrupting (burst length = 4 or 8) on page 39 to write to precharge: nominal dqss (2 bit write), interrupting (burst length = 4 or 8) on page 41. note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data in should be masked with dm. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a write burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with auto pre- charge. the disadvantage of the precharge command is that it requires that the command and address bus- ses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
hyb25d256400/800at 256-mbit double data rate sdram page 29 of 75 10/01 write command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don ? t care ca x4: a0-a9, a11 x8: a0-a9 x16: a0-a8 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
hyb25d256400/800at 256-mbit double data rate sdram page 30 of 75 10/01 write burst (burst length = 4) t1 t2 t3 t4 t dqss (max) nop nop nop write di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. a10 is low with the write command (auto precharge is disabled). ck ck command address dqs dq dm don ? t care maximum dqss ba a, col b t1 t2 t3 t4 t dqss (min) nop nop nop write ck ck command address dqs minimum dqss ba a, col b dq dm dla-b dla-b
hyb25d256400/800at 256-mbit double data rate sdram page 31 of 75 10/01 write to write (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss nop write nop nop nop write di a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don ? t care t1 t2 t3 t4 t5 t6 minimum dqss nop write nop nop nop write ck ck command address dqs dq dm baa, col b baa, col n ba, col b ba, col n t dqss (min) di a-b di a-n di a-b di a-n
hyb25d256400/800at 256-mbit double data rate sdram page 32 of 75 10/01 write to write: max dqss, non-consecutive (burst length = 4) t1 t2 t3 t4 t5 t dqss (max) nop nop write nop write di a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don ? t care baa, col b baa, col n di a-b di a-n
hyb25d256400/800at 256-mbit double data rate sdram page 33 of 75 10/01 random write cycles (burst length = 2, 4 or 8) t1 t2 t3 t4 t5 t dqss (max) maximum dqss write write write write write di a-b di a-n di a-b, etc. = data in for bank a, column b, etc. b ? , etc. = odd or even complement of b, etc. (i.e., column address lsb inverted). each write command may be to any bank. di a-b ? di a-x di a-x ? di a-n ? di a-a di a-a ? ck ck command address dqs dq dm don ? t care baa, col b baa, col x baa, col n baa, col a baa, col g t1 t2 t3 t4 t5 minimum dqss write write write write write di a-b di a-n di a-b ? di a-x di a-x ? di a-n ? di a-a di a-a ? ck ck command address dqs dq dm baa, col b baa, col x baa, col n baa, col a baa, col g t dqss (min) di a-g
hyb25d256400/800at 256-mbit double data rate sdram page 34 of 75 10/01 write to read: non-interrupting (cas latency = 2; burst length = 4) cl = 2 t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write di a-b nop di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wtr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write command (auto precharge is disabled). the read and write commands may be to any bank. ck ck command address dqs dq dm don ? t care maximum dqss baa, col b baa, col n t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write nop ck ck command address minimum dqss baa, col b baa, col n t dqss (max) di a-b dqs dq dm t dqss (min) cl = 2
hyb25d256400/800at 256-mbit double data rate sdram page 35 of 75 10/01 write to read: interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. dia- b ck ck command address dqs dq dm don ? t care baa, col b baa, col n t wtr cl = 2 t1 t2 t3 t4 t5 t6 minimum dqss nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq dm cl = 2 t dqss (min) 1 = these bits are incorrectly written into the memory array if dm is low. 11 11
hyb25d256400/800at 256-mbit double data rate sdram page 36 of 75 10/01 write to read: minimum dqss, odd number of data (3 bit write), interrupting (cas latency = 2; burst length = 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair (not the last desired data in element) the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. don ? t care t1 t2 t3 t4 t5 t6 nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq cl = 2 t dqss (min) dm 122 1 = this bit is correctly written into the memory array if dm is low. 2 = these bits are incorrectly written into the memory array if dm is low.
hyb25d256400/800at 256-mbit double data rate sdram page 37 of 75 10/01 write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (nom) nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. di a-b ck ck command address dqs dq dm don ? t care baa, col b baa, col n t wtr cl = 2 1 = these bits are incorrectly written into the memory array if dm is low. 1 1
hyb25d256400/800at 256-mbit double data rate sdram page 38 of 75 10/01 write to precharge: non-interrupting (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) nop nop nop nop write di a-b pre di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write command (auto precharge is disabled). ck ck command address dqs dq dm don ? t care ba a, col b ba (a or all) t wr maximum dqss t1 t2 t3 t4 t5 t6 nop nop nop nop write pre ck ck command address ba a, col b ba (a or all) t wr minimum dqss di a-b dqs dq dm t dqss (min) t rp t rp
hyb25d256400/800at 256-mbit double data rate sdram page 39 of 75 10/01 write to precharge: interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst, for burst length = 8. a10 is low with the write command (auto precharge is disabled). 1 = can be don ? t care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don ? t care at this point. don ? t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address maximum dqss di a-b 11 2 dqs dq dm t dqss (max) t rp t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) minimum dqss t wr t rp di a-b 11 dqs dq dm t dqss (min) 2 ba a, col b ba (a or all) t wr 3 = these bits are incorrectly written into the memory array if dm is low. 3 3 3 3
hyb25d256400/800at 256-mbit double data rate sdram page 40 of 75 10/01 write to precharge: minimum dqss, odd number of data (1 bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 1 data element is written. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). 1 = can be don ? t care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don ? t care at this point. don ? t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t wr t rp di a-b dqs dq t dqss (min) 2 11 dm 344 3 = this bit is correctly written into the memory array if dm is low. 4 = these bits are incorrectly written into the memory array if dm is low.
hyb25d256400/800at 256-mbit double data rate sdram page 41 of 75 10/01 write to precharge: nominal dqss (2 bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). 1 = can be don ? t care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don ? t care at this point. don ? t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t rp t dqss (nom) di a-b 1 2 dqs dq dm 1 t wr 3 3 3 = these bits are incorrectly written into the memory array if dm is low.
hyb25d256400/800at 256-mbit double data rate sdram page 42 of 75 10/01 precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time (t rp ) after the precharge com- mand is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ? don ? t care. ? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. precharge command ba high ba = bank address ck ck cke cs ras cas we a10 ba0, ba1 don ? t care all banks one bank (if a10 is low, otherwise don ? t care). a0-a9, a11, a12
hyb25d256400/800at 256-mbit double data rate sdram page 43 of 75 10/01 power-down power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding ck, ck and cke. the dll is still running in power down mode, so for maximum power savings, the user has the option of disabling the dll prior to entering power- down. in that case, the dll must be enabled after exiting power-down, and 200 clock cycles must occur before a read command can be issued. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, and all other input signals are ? don ? t care ? . however, power- down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the dll-disabled power-down mode. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command may be applied one clock cycle later. power down t is t is ck ck cke command no column access in progress valid nop valid don ? t care exit power down mode enter power down mode (burst read or write operation must not be in progress) nop
hyb25d256400/800at 256-mbit double data rate sdram page 44 of 75 10/01 truth table 2: clock enable (cke) 1. cken is the logic state of cke at clock edge n: cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock edge n, and action n is a result of command n. 4. all states and sequences not shown are illegal or reserved. current state cke n-1 cken command n action n notes previous cycle current cycle self refresh l l x maintain self-refresh self refresh l h deselect or nop exit self-refresh 1 power down l l x maintain power-down power down l h deselect or nop exit power-down all banks idle h l deselect or nop precharge power-down entry all banks idle h l auto refresh self refresh entry bank(s) active h l deselect or nop active power-down entry hh see ? truth table 3: current state bank n - command to bank n (same bank) ? on page 45 1. deselect or nop commands should be issued on any clock edges occurring during the self refresh exit (t xsnr ) period. a mini- mum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock.
hyb25d256400/800at 256-mbit double data rate sdram page 45 of 75 10/01 truth table 3: current state bank n - command to bank n (same bank) (part 1 of 2) current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation 1-6 l h h h no operation nop. continue previous operation 1-6 idle l l h h active select and activate row 1-6 lllh auto refresh 1-7 l l l l mode register set 1-7 row active l h l h read select column and start read burst 1-6, 10 l h l l write select column and start write burst 1-6, 10 l l h l precharge deactivate row in bank(s) 1-6, 8 read (auto precharge disabled) l h l h read select column and start new read burst 1-6, 10 l l h l precharge truncate read burst, start precharge 1-6, 8 l h h l burst terminate burst terminate 1-6, 9 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are th ose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ? row active ? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to truth table 4. 5. the following states must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ? all banks idle ? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ? all banks idle ? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking.
hyb25d256400/800at 256-mbit double data rate sdram page 46 of 75 10/01 write (auto precharge disabled) l h l h read select column and start read burst 1-6, 10, 11 l h l l write select column and start write burst 1-6, 10 l l h l precharge truncate write burst, start precharge 1-6, 8, 11 truth table 3: current state bank n - command to bank n (same bank) (part 2 of 2) current state cs ras cas we command action notes 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are th ose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ? row active ? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to truth table 4. 5. the following states must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ? all banks idle ? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ? all banks idle ? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking.
hyb25d256400/800at 256-mbit double data rate sdram page 47 of 75 10/01 truth table 4: current state bank n - command to bank m (different bank) (part 1 of 2) current state cs ras cas we command action notes any h x x x deselect nop/continue previous operation 1-6 l h h h no operation nop/continue previous operation 1-6 idle xxxx any command otherwise allowed to bank m 1-6 row activating, active, or precharging l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-7 l h l l write select column and start write burst 1-7 l l h l precharge 1-6 read (auto precharge disabled) l l h h active select and activate row 1-6 l h l h read select column and start new read burst 1-7 l l h l precharge 1-6 write (auto precharge disabled) l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-8 l h l l write select column and start new write burst 1-7 l l h l precharge 1-6 read (with auto precharge) l l h h active select and activate row 1-6 l h l h read select column and start new read burst 1-7,10 l h l l write select column and start write burst 1-7,9,10 l l h l precharge 1-6 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands sho wn are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). excep- tions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see note 10. write with auto precharge enabled: see note 10. 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output. 10. concurrent auto precharge: this device supports ? concurrent auto precharge ? . when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between read data and write data must be avoided). the mimimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 4a.
hyb25d256400/800at 256-mbit double data rate sdram page 48 of 75 10/01 truth table 4a : concurrent auto precharge: write (with auto precharge) l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-7,10 lhll write select column and start new write burst 1-7,10 l l h l precharge 1-6 from command to command (different bank) minimum delay with con- current auto precharge support units write w/ap read or read w/ap 1 + (bl/2) + twtr tck write ot write w/ap bl/2 tck precharge or activate 1 tck read w/ap read or read w/ap bl/2 tck write or write w/ap cl (rounded up)+ bl/2 tck precharge or activate 1 tck truth table 4: current state bank n - command to bank m (different bank) (part 2 of 2) current state cs ras cas we command action notes 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands sho wn are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). excep- tions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see note 10. write with auto precharge enabled: see note 10. 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output. 10. concurrent auto precharge: this device supports ? concurrent auto precharge ? . when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between read data and write data must be avoided). the mimimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 4a.
hyb25d256400/800at 256-mbit double data rate sdram page 49 of 75 10/01 simplified state diagram self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a burst stop preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge
hyb25d256400/800at 256-mbit double data rate sdram page 50 of 75 10/01 operating conditions absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to v ss ? 0.5 to v ddq + 0.5 v v in voltage on inputs relative to v ss ? 0.5 to + 3.6 v v dd voltage on v dd supply relative to v ss ? 0.5 to + 3.6 v v ddq voltage on v ddq supply relative to v ss ? 0.5 to + 3.6 v t a operating temperature (ambient) 0 to + 70 c t stg storage temperature (plastic) ? 55 to + 150 c p d power dissipation 1.0 w i out short circuit output current 50 ma note: stresses greater than those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operat ional sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli ability. input and output capacitances parameter symbol min. max. units notes input capacitance: ck, ck c i1 2.0 3.0 pf 1 delta input capacitance c di1 -0.25pf1 input capacitance: all other input-only pins c i2 2.0 3.0 pf 1 input/output capacitance: dq, dqs, dm c io 4.0 5.0 pf 1, 2 delta input/output capacitance : dq, dqs, dm c dio -0.5pf1 1. these values are guaranteed by design and are tested on a sample base only. v ddq = v dd = 2.5v 0.2v, f = 100mhz, t a = 25 c, v out (dc) = v ddq/2 , vout (peak to peak) 0.2v. unused pins are tied to groundvout (peak to peak) = 0.2v. 2. dm inputs are grouped with i/o pins reflecting the fact that they are matched in loading to dq and dqs to facilitate trace ma tching at the board level.
hyb25d256400/800at 256-mbit double data rate sdram page 51 of 75 10/01 dc electrical operating conditions (0c t a 70 c; v d dq = 2.5v 0.2v, v dd = + 2.5v 0.2v) symbol parameter min max units notes v dd supply voltage 2.3 2.7 v 1 v ddq i/o supply voltage 2.3 2.7 v 1 v ss , v ssq supply voltage, i/o supply voltage 0 0 v v ref i/o reference voltage 0.49 x v ddq 0.51 x v ddq v1, 2 v tt i/o termination voltage (system) v ref ? 0.04 v ref + 0.04 v 1, 3 v ih(dc) input high (logic1) voltage v ref + 0.18 v ddq + 0.3 v 1 v il(dc) input low (logic0) voltage ? 0.3 v ref ? 0.18 v 1 v in(dc) input voltage level, ck and ck inputs ? 0.3 v ddq + 0.3 v 1 v id(dc) input differential voltage, ck and ck inputs 0.36 v ddq + 0.6 v 1, 4 vi ratio vi-matching pullup current to pulldown current 0.71 1.4 5 i i input leakage current any input 0v v in v dd (all other pins not under test = 0v) ? 22 a1 i oz output leakage current (dqs are disabled; 0v v out v ddq) ? 55 a1 i oh output high current, normal strength driver (v out = 1.95 v) ? 15.2 ma 1 i ol output low current, normal strength driver (v out = 0.35 v)) 15.2 ma 1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to- peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck . 5. the ration of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire t empera- ture and voltage range, for device drain to source voltage from 0.25 to 1.0v. for a given output, it represents the maximum dif fer- ence between pullup and pulldown drivers due to process variation.
hyb25d256400/800at 256-mbit double data rate sdram page 52 of 75 10/01 pulldown and pullup characteristics 1. the nominal pulldown v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve. 2. the full variation in driver pulldown current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v-i curve. 3. the nominal pullup v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve. 4. the full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v-i curve. 5. the full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. the full variation in the ratio of the nominal pullup to pulldown current should be unity 10 % , for device drain to source voltages from 0.1 to 1.0v. pulldown characteristics pullup characteristics 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 120 140 1 out (ma) v out (v) maximum nominal high nominal low minimum maximum nominal high nominal low minimum v out (v) 0.5 1 1.5 2 2.5 0 0 -20 -40 -60 -80 -100 -120 -140 -160 1 out (ma)
hyb25d256400/800at 256-mbit double data rate sdram page 53 of 75 10/01 the above characteristics are specified under best, worst, and nominal process variations / conditions. pulldown and pullup currents pulldown current (ma) pullup current (ma) voltage (v) nominal low nominal high min max nominal low nominal high min max 0.16.06.84.69.6 ? 6.1 ? 7.6 ? 4.6 ? 10.0 0.2 12.2 13.5 9.2 18.2 ? 12.2 ? 14.5 ? 9.2 ? 20.0 0.3 18.1 20.1 13.8 26.0 ? 18.1 ? 21.2 ? 13.8 ? 29.8 0.4 24.1 26.6 18.4 33.9 ? 24.0 ? 27.7 ? 18.4 ? 38.8 0.5 29.8 33.0 23.0 41.8 ? 29.8 ? 34.1 ? 23.0 ? 46.8 0.6 34.6 39.1 27.7 49.4 ? 34.3 ? 40.5 ? 27.7 ? 54.4 0.7 39.4 44.2 32.2 56.8 ? 38.1 ? 46.9 ? 32.2 ? 61.8 0.8 43.7 49.8 36.8 63.2 ? 41.1 ? 53.1 ? 36.0 ? 69.5 0.9 47.5 55.2 39.6 69.9 ? 43.8 ? 59.4 ? 38.2 ?77.3 1.0 51.3 60.3 42.6 76.3 ? 46.0 ? 65.5 ? 38.7 ? 85.2 1.1 54.1 65.2 44.8 82.5 ? 47.8 ? 71.6 ? 39.0 ? 93.0 1.2 56.2 69.9 46.2 88.3 ? 49.2 ? 77.6 ? 39.2 ? 100.6 1.3 57.9 74.2 47.1 93.8 ? 50.0 ? 83.6 ? 39.4 ? 108.1 1.4 59.3 78.4 47.4 99.1 ? 50.5 ? 89.7 ? 39.6 ? 115.5 1.5 60.1 82.3 47.7 103.8 ? 50.7 ? 95.5 ? 39.9 ? 123.0 1.6 60.5 85.9 48.0 108.4 ? 51.0 ? 101.3 ? 40.1 ? 130.4 1.7 61.0 89.1 48.4 112.1 ? 51.1 ? 107.1 ? 40.2 ? 136.7 1.8 61.5 92.2 48.9 115.9 ? 51.3 ? 112.4 ? 40.3 ? 144.2 1.9 62.0 95.3 49.1 119.6 ? 51.5 ? 118.7 ? 40.4 ? 150.5 2.0 62.5 97.2 49.4 123.3 ? 51.6 ? 124.0 ? 40.5 ? 156.9 2.1 62.9 99.1 49.6 126.5 ? 51.8 ? 129.3 ? 40.6 ? 163.2 2.2 63.3 100.9 49.8 129.5 ? 52.0 ? 134.6 ? 40.7 ? 169.6 2.3 63.8 101.9 49.9 132.4 ? 52.2 ? 139.9 ? 40.8 ? 176.0 2.4 64.1 102.8 50.0 135.0 ? 52.3 ? 145.2 ? 40.9 ? 181.3 2.5 64.6 103.8 50.2 137.3 ? 52.5 ? 150.5 ? 41.0 ? 187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 pulldown and pullup process variations and conditions nominal minimum maximum operating temperature 25 c0 c70 c v dd / v ddq 2.5v 2.3v 2.7v
hyb25d256400/800at 256-mbit double data rate sdram page 54 of 75 10/01 idd specification and conditions (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2) symbol parameter/condition ddr200 ddr266a unit notes typ. max typ. max 4) i dd0 operating current : one bank; active / precharge; t rc = t rc min ; t ck = t ck min ; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 71 90 76 100 ma 1, 2 i dd1 operating current : one bank; active / read / precharge; burst = 4; refer to the following page for detailed test conditions. 88 100 97 120 ma 1, 2 i dd2p precharge power-down standby current : all banks idle; power-down mode; cke v il max ; t ck = t ck min 11.3 15 13.5 20 ma 1, 2 i dd2f precharge floating standby current : cs v ih min , all banks idle; cke v il max ; t ck = t ck min ,address and other control inputs changing once per clock cycle, v in = v ref for dq, dqs and dm. 25.2353135 ma 1, 2 i dd2q precharge quiet standby current : cs v ih min , all banks idle; cke v ih min ; t ck = t ck min ,address and other control inputs stable at v ih min or v il max ; v in = v ref for dq, dqs and dm. 24.7 35 30.4 40 ma 1, 2 i dd3p active power-down standby current : one bank active; power-down mode; cke v il max ; t ck = t ck min ;v in = v ref for dq, dqs and dm. 11.4 15 13.5 20 ma 1, 2 i dd3n active standby current : one bank active; active / pre- charge;cs v ih min ; cke v ih min ; t rc = t ras max ; t ck = t ck min ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 45 60 54 70 ma 1, 2 i dd4r operating current: one bank active; burst = 2; reads; continu- ous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2 for ddr200 and ddr266a, t ck = t ck min ; i out = 0ma 105 150 134 190 ma 1, 2 i dd4w operating current : one bank active; burst = 2; writes; continu- ous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl = 2 for ddr200 and ddr266a, t ck = t ck min 91 130 115 170 ma 1, 2 i dd5 auto-refresh current : t rc = t rfc min, distributed refresh 130 180 142 190 ma 1, 2 i dd6 self-refresh current : cke 0.2v; external clock on; t ck = t ck min 1.8 3 1.8 3 ma 1, 2, 3 i dd7 operating current: four bank; four bank interleaving with bl=4. refer to the following page for detailed test conditions 192 250 246 300 ma 1, 2 1. i dd specifications are tested after the device is properly initialized and measured at 100 mhz for ddr200 and 133 mhz for ddr266. 2. input slew rate = 1v/ns . 3. enables on-chip refresh and address counters 4. test condition for typical values : v dd = 2.5v ,ta = 25 o c, test condition for maximum values: test limit at v dd = 2.7v ,ta = 10 o c
hyb25d256400/800at 256-mbit double data rate sdram page 55 of 75 10/01 detailed test conditions for idd1 and idd7 idd1 : operating current : one bank operation 1. only one bank is accessed with t rc(min) , burst mode, address and control inputs on nop edge are changing once per clock cycle. l out = 0 ma 2. timing patterns - ddr200 (100mhz, cl=2) : tck = 10 ns, cl=2, bl=4, trcd = 2 * tck, tras = 5 * tck setup: a0 n r0 n n p0 n read : a0 n r0 n n p0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5 ns, cl=2, bl=4, trcd = 3 * tck, trc = 9 * tck, tras = 5 * tck setup: a0 n n r0 n p0 n n n read : a0 n n r0 n p0 n nn - repeat the same timing with random address changing 50% of data changing at every burst 3.legend : a=activate, r=read, w=write, p=precharge, n=nop idd7 : operating current: four bank operation 1. four banks are being interleaved with t rc(min) , burst mode, address and control inputs on nop edge are not changing. l out = 0 ma 2. timing patterns - ddr200 (100mhz, cl=2) : tck = 10 ns, cl=2, bl=4, trrd = 2 * tck, trcd= 3 * tck, read with autoprecharge setup: a0 n a1 r0 a2 r1 a3 r2 read : a0 r3 a1 r0 a2 r1 a3 r2- repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5 ns, cl=2, bl=4, trrd = 2 * tck, trcd = 3 * tck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read : a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every burst 3.legend : a=activate, r=read, w=write, p=precharge, n=nop
hyb25d256400/800at 256-mbit double data rate sdram page 56 of 75 10/01 ac characteristics ac operating conditions (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) see notes 5 ~ 11. symbol parameter/condition min max unit notes v ih(ac) input high (logic 1) voltage, dq, dqs, and dm signals v ref + 0.35 v 1, 2 v il(ac) input low (logic 0) voltage, dq, dqs, and dm signals v ref ? 0.35 v 1, 2 v id(ac) input differential voltage, ck and ck inputs 0.7 v ddq + 0.6 v 1, 2, 3 v ix(ac) input closing point voltage, ck and ck inputs 0.5*v ddq ? 0.2 0.5*v ddq + 0.2 v 1, 2, 4 1. input slew rate = 1v/ns . 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 5. all voltages referenced to v ss . 6. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 7. the figure below represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a produ ction tester. system designers will use ibis or other simulation tools to correlate the timing reference load to a system environment . manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the teste r elec- tronics). 8. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v ih(ac) . 9. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a r esult of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level. 10. for system characteristics like setup & holdtime derating for slew rate, i/o delta rise/fall derating,ddr sdram slew rate standards, overshoot & undershoot specification and clamp v-i characteristics see the latest jedec specification for ddr com- ponents 11. notes 5-10 apply to the following tables: electrical characteristics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and electrical characteristics and ac timing.) ac output load circuit diagram / timing reference load 50 ? timing reference point output (v out ) 30pf v tt
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 57 of 75 electrical characteristics & ac timing for ddr266/ddr200 - absolute specifications (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) (part 1 of 3) symbol parameter ddr266a -7 ddr200 -8 unit notes min max min max t ac dq output access time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4 t dqsck dqs output access time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4 t ch ck high-level width 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 t ck 1-4 t hp clock half period min (t cl, t ch) min (t cl, t ch) ns 1-4 t ck clock cycle time cl = 2.5 7 12 8 12 ns 1-4 t ck cl = 2.0 7.5 12 10 12 ns 1-4 t dh dq and dm input hold time 0.5 0.6 ns 1-4 t ds dq and dm input setup time 0.5 0.6 ns 1-4 t ipw control and addr. input pulse width (each input) 2.2 2.5 ns 1-4,10 t dipw dq and dm input pulse width (each input) 1.75 2 ns 1-4,10 t hz data-out high-impedence time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4, 5 t lz data-out low-impedence time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4, 5 t dqss write command to 1st dqs latching transition 0.75 1.25 0.75 1.25 t ck 1-4 t dqsq dqs-dq skew (for dqs & associated dq signals) + 0.5 + 0.6 ns 1-4 t qhs data hold skew factor + 0.75 + 1.0 ns 1-4 t qh data output hold time from dqs t hp -t qhs t hp -t qhs ns 1-4 1. input slew rate >=1v/ns for ddr266 and = 1v/ns for ddr200. 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. ck/ck slew rate are >= 1.0 v/ns. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. for each of the terms, if not already an integer, round to the next highest integer. tck is equal to the actual sys- tem clock cycle time. 10. these parameters guarantee device timing, but they are not necessarily tested on each device 11. fast slew rate >= 1.0 v/ns , slow slew rate >= 0.5 v/ns and < 1v/ns for command/address and ck & ck slew rate >1.0 v/ns, measured between voh(ac) and vol(ac)
hyb25d256400/800at 256-mbit double data rate sdram page 58 of 75 10/01 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 t ck 1-4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 14 16 ns 1-4 t wpres write preamble setup time 0 0 ns 1-4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 t ck 1-4, 6 t wpre write preamble 0.25 0.25 t ck 1-4 t is address and control input setup time fast slew rate 0.9 1.1 ns 2-4, 10,11 slow slew rate 1.0 1.1 ns t ih address and control input hold time fast slew rate 0.9 1.1 ns slow slew rate 1.0 1.1 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck 1-4 t rpst read postamble 0.40 0.60 0.40 0.60 t ck 1-4 t ras active to precharge command 45 120,000 50 120,000 ns 1-4 t rc active to active/auto-refresh command period 65 70 ns 1-4 t rfc auto-refresh to active/auto-refresh command period 75 80 ns 1-4 t rcd active to read or write delay 20 20 ns 1-4 t rp precharge command period 20 20 ns 1-4 electrical characteristics & ac timing for ddr266/ddr200 - absolute specifications (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) (part 2 of 3) symbol parameter ddr266a -7 ddr200 -8 unit notes min max min max 1. input slew rate >=1v/ns for ddr266 and = 1v/ns for ddr200. 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. ck/ck slew rate are >= 1.0 v/ns. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. for each of the terms, if not already an integer, round to the next highest integer. tck is equal to the actual sys- tem clock cycle time. 10. these parameters guarantee device timing, but they are not necessarily tested on each device 11. fast slew rate >= 1.0 v/ns , slow slew rate >= 0.5 v/ns and < 1v/ns for command/address and ck & ck slew rate >1.0 v/ns, measured between voh(ac) and vol(ac)
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 59 of 75 t rrd active bank a to active bank b command 15 15 ns 1-4 t wr write recovery time 15 15 ns 1-4 t dal auto precharge write recovery + precharge time (twr/tck) + (trp/tck) t ck 1-4, 9 t wtr internal write to read command delay 1 1 t ck 1-4 t xsnr exit self-refresh to non-read command 75 80 ns 1-4 t xsrd exit self-refresh to read command 200 200 t ck 1-4 t refi average periodic refresh interval 7.8 7.8 s1-4, 8 electrical characteristics & ac timing for ddr266/ddr200 - absolute specifications (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) (part 3 of 3) symbol parameter ddr266a -7 ddr200 -8 unit notes min max min max 1. input slew rate >=1v/ns for ddr266 and = 1v/ns for ddr200. 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. ck/ck slew rate are >= 1.0 v/ns. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. for each of the terms, if not already an integer, round to the next highest integer. tck is equal to the actual sys- tem clock cycle time. 10. these parameters guarantee device timing, but they are not necessarily tested on each device 11. fast slew rate >= 1.0 v/ns , slow slew rate >= 0.5 v/ns and < 1v/ns for command/address and ck & ck slew rate >1.0 v/ns, measured between voh(ac) and vol(ac)
hyb25d256400/800at 256-mbit double data rate sdram page 60 of 75 10/01 electrical characteristics & ac timing for ddr266a - applicable specifications expressed in clock cycles (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) symbol parameter ddr266a @ cl=2.5 units notes min max t mrd mode register set command cycle time 2 t ck 1-5 t wpre write preamble 0.25 t ck 1-5 t ras active to precharge command 6 16000 t ck 1-5 t rc active to active/auto-refresh command period 9 t ck 1-5 t rfc auto-refresh to active/auto-refresh command period 10 t ck 1-5 t rcd active to read or write delay 3 t ck 1-5 t rp precharge command period 3 t ck 1-45 t rrd active bank a to active bank b command 2 t ck 1-5 t wr write recovery time 2 t ck 1-5 t dal auto precharge write recovery + precharge time 5 t ck 1-5 t wtr internal write to read command delay 1 t ck 1-5 t xsnr exit self-refresh to non-read command 10 t ck 1-5 t xsrd exit self-refresh to read command 200 t ck 1-5 1. input slew rate = 1v/ns 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a spe- cific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz).
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 61 of 75 timing diagrams data input (write) (timing burst length = 4) data output (read) (timing burst length = 4) t dh t ds t dh t ds t dqsl di n = data in for column n. 3 subsequent elements of data in are applied in programmed order following di n. di n dqs dq dm don ? t care t dqsh t qh (data output hold time from dqs) t dqsq and t qh are only shown once and are shown referenced to different edges of dqs, only for clarify of illustration. . dqs dq t dqsq max t qh t dqsq and t qh both apply to each of the four relevant edges of dqs. t dqsq max. is used to determine the worst case setup time for controller data capture. t qh is used to determine the worst case hold time for controller data capture.
hyb25d256400/800at 256-mbit double data rate sdram page 62 of 75 10/01 initialize and mode register sets t ih 200 s t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t mrd t rfc t rfc t rp t mrd t mrd t cl t ck t ch t vtd pre emrs mrs pre ar ar mrs nop act code code code ra code code code ra ba0=l ba0=l ba high-z high-z power-up: vdd and ck stable extended mode register set load mode register, reset dll load mode register (with a8 = l) vdd vddq vtt (system * ) vref ck cke command dm a0-a9, a11 a10 ba0, ba1 dqs dq lvcmos low level all banks ba0=h ba1=l ba1=l ba1=l all banks * vtt is not applied directly to the device, however t vtd must be ** t mrd is required before any command can be applied and the two autorefresh commands may be moved to follow the first mrs, greater than or equal to zero to avoid device latchup. 200 cycles of ck are required before a read command can be applied. but precede the second precharge all command. don ? t care 200 cycles of ck ** ck
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 63 of 75 power down mode t ih t is t ih t is t is t is t ih t is t cl t ch t ck nop valid valid * valid valid enter power down mode exit power down mode no column accesses are allowed to be in progress at the time power down is entered. * = if this command is a precharge (or if the device is already in the idle state) then the power down mode shown is precharge power down. if this command is an active (or if at least one row is already active), then the power down mode shown is active power down. cke command addr dqs dq dm don ? t care c k c k nop
hyb25d256400/800at 256-mbit double data rate sdram page 64 of 75 10/01 auto refresh mode t ih t is t ih t is t ih t is t rfc t rp t cl t ch t ck pre nop nop ar nop ar nop nop nop ra ra ba pre = precharge; act = active; ra = row address; ba = bank address; ar = autorefresh. nop commands are shown for ease of illustration; other valid commands may be possible at these times. dm, dq, and dqs signals are all don ? t care/high-z for operations shown. valid valid act ra cke command a0-a8 a9, a11,a12 a10 ba0, ba1 dqs dq dm bank(s) don ? t care all banks one bank t rfc ck ck
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 65 of 75 self refresh mode 200 cycles t ih t is t xsrd, t xsrn t ih t is t is t is t ih t is t rp * t ck t cl t ch ar valid nop valid enter self refresh mode exit self refresh mode nop * = device must be in the all banks idle state before entering self refresh mode. ** = t xsnr is required before any non-read command can be applied, and t xsrd (200 cycles of ck). cke command addr dqs dq dm don ? t care are required before a read command can be applied. ck ck clock must be stable before exiting self refresh mode
hyb25d256400/800at 256-mbit double data rate sdram page 66 of 75 10/01 read without auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck pre nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. * = don ? t care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x ba x valid valid valid nop read col n ra ra ba x * do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 all banks one bank t dqsck (max) t rpre cl=2 t rpre don ? t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n c k c k dis ap dis ap = disable auto precharge.
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 67 of 75 read with auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck nop nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. en ap = enable auto precharge. act = active; ra = row address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x valid valid valid nop read col n ra ra do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 t dqsck (max) t rpre cl=2 t rpre don ? t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n en ap ba x c k c k t hz (min)
hyb25d256400/800at 256-mbit double data rate sdram page 68 of 75 10/01 bank read access (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck read nop pre nop nop act nop nop ba x ba x* valid nop act ra ra ba x do n c k c k cke command a10 ba0, ba1 dm dqs dq dqs dq t dqsck (max) t rpre cl=2 cl=2 t rpre don ? t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n col n ra ra all banks ra one bank dis ap ba x t rp do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. dis ap = disable auto precharge. * = don ? t care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. t rcd a0-a9, a11, a12 t ras t rc t lz (min)
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 69 of 75 write without auto precharge (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t rp t cl t ch t ck nop nop nop pre nop nop act nop ba x ba nop write col n ra ra ba x * valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. dis ap = disable auto precharge. * = don ? t care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. din c k c k cke command a10 ba0, ba1 dqs dq dm dis ap all banks one bank t wr t wpres t dqsh don ? t care a0-a9, a11, a12 t dqss = min. t dqss t wpre t dsh
hyb25d256400/800at 256-mbit double data rate sdram page 70 of 75 10/01 write with auto precharge (burst length = 4) nop commands are shown for ease of illustration; other valid commands may be possible at these times. act = active; ra = row address; ba = bank address. t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop nop nop nop act nop ba x ba nop write col n ra ra valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. en ap = enable auto precharge. c k c k cke command a10 ba0, ba1 dqs dq dm t wr t dqss t wpres t dqsh don ? t care valid valid en ap a0-a9, a11, a12 t dal t dqss = min. t dsh t wpre din
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 71 of 75 bank write access (burst length = 4) t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck t ras write nop nop nop nop pre nop nop ba x nop act ra ra di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n. dis ap = disable auto precharge. * = don ? t care if a10 is high at this point. pre = precharge; act = active; ra = row address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. din valid ba x cke command a10 ba0, ba1 dqs dq dm ck ck t wpres t wr t rcd all banks one bank dis ap don ? t care a0-a9, a11, a12 col n ba x t dqss t dqsh t dsh t wpre t dqss = min.
hyb25d256400/800at 256-mbit double data rate sdram page 72 of 75 10/01 write dm operation (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop pre nop nop act nop nop write col n ra din ck ck cke command a10 ba0, ba1 dqs dq dm t wr t dqss don ? t care valid t ih t is t ih t is ba x ba ra ba x * all banks one bank dis ap di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n (the second element of the 4 is masked). dis ap = disable auto precharge. * = don ? t care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. a0-a9, a11, a12 t dqsh t dsh t dqss = min. t wpres
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 73 of 75 package dimensions (400mil; 66 lead; thin small outline package) plastic package, p-tsopii-66 (400mil; 66 lead ) thin small outline package tsop66 0,65 basic 0,3 0,08 0,805 ref 0,05 min 1,20 max 22,220,13 lead #1 10,160,13 0,50,1 11,760,2 0.1 0,25 basic gauge plane seating plane
hyb25d256400/800at 256-mbit double data rata sdram 10/01 page 74 of 75 table of content features 1 description 1 pin configuration 2 input/output functional description 3 block diagram (32mb x 4) 5 block diagram (16mb x 8) 6 functional description 7 initialization 7 register definition 8 mode register operation 9 burst definition 10 required cas latencies 11 extended mode register 12 extended mode register definition 13 commands 14 delesect, no operation 14 mode register set 14 active 14 read 14 write 14 precharge 14 auto precharge 15 burst terminate 15 auto refresh 15 self refresh 15 truth table 1a: commands 16 truth table 1b: dm operation 16 operations 17 activating a specific row in a specific bank 17 trcd and trrd definition 18 read command 19 read burst 20 consecutive read bursts 21 non-consecutive read bursts 22 random read accesses 23 terminating a read burst 25 read to write 26 read to precharge 27 write command 28 write burst (burst length = 4) 30 write to write (burst length = 4) 31 write to write 32 random write cycles 33 write to read 34 write to read interrupting 35 write to read: minimum dqss 36 write to read: nominal dqss 37 write to precharge non-interrupting 38 write to precharge interrupting 39 write to precharge minimum dqss 40 write to precharge: nominal dqss 41 precharge 42 power-down 43 truth table 2: clock enable (cke) 44 truth table 3: current state, samebank) 45 truth table 4: current state,different bank 47 simplified state diagram 49 operating conditions 50 absolute maximum ratings 50 input and output capacitances 50 dc electrical operating conditions 51 pulldown characteristics 52 pullup characteristics 52 pulldown and pullup currents 53 idd specifications and conditions 54 ac characteristics 56 ac output load circuit diagram 56 electrical characteristics & ac timing 57 timing diagrams 61 data input (write) 61 data output (read) 61 initialize and mode register sets 62 power down mode 63 auto refresh mode 64 self refresh mode 65 read without auto precharge 66 read with auto precharge 67 bank read access 68 write without auto precharge. 69 write with auto precharge 70 bank write access 71 write dm operation 72 package dimensions 73 table of content 74 secuity information 75
hyb25d256400/800at 256-mbit double data rate sdram 10/01 page 75 of 75 attention please ! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. this infomation describes the type of components and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact infineon technologies offices in munich or the infineon technologies sales offices and representatives worldwide. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office or representative. packing please use the recycling operators known to you. we can help you - get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! ciritcal components 1 of infineon technologies, may only be used in life- support devices or systems 2 with the express written approval of infineon technologies. 1. a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect the safety or effectiveness of that device or system. 2. life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.

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